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Additional resources for Analog and Mixed-Signal Modeling Using the VHDL-AMS Language [Presentation Slides, 36 Design Conference]
Q’Delayed(T) • Quantity Q delayed by T (ideal delay, T >= 0) @8u vrÃF7hxhyh Ã6H9rrÃ@Hr 968((ÃWC9G6HTÃU vhy VHDL AMS Implicit Quantities (2) ♦ Q’Ltf(num, den) • Laplace transfer function whose input is Q ♦ Q’ZOH(T, initial_delay) • A sampled version of quantity Q (zero-order hold) ♦ Q’Ztf(num, den, T, initial_delay) • Z-domain transfer function whose input is Q ♦ S’Ramp(tr, tf) • A quantity that follows signal S, but with specified rise and fall times. t. time is limited by the specified slopes.
End architecture Proc; ♦ Branch quantities vp and vm are composite because terminals inp and inm are composite @8u vrÃF7hxhyh Ã6H9rrÃ@Hr 968((ÃWC9G6HTÃU vhy VHDL AMS Generic Weighted Summer VHDL-AMS Architecture Body: Statements ♦ Using a simultaneous procedural statement ... 0; begin for i in beta’range loop bvs := bvs + beta(i) * vp(i); end loop; for i in gamma’range loop gvs := gvs + gamma(i) * vm(i); end loop; vo := bvs - gvs; end procedural; end architecture Proc; ♦ Allows writing equations using a sequential language • Supports all sequential statements except wait, signal assignment, break @8u vrÃF7hxhyh Ã6H9rrÃ@Hr 968((ÃWC9G6HTÃU vhy VHDL AMS Generic Weighted Summer VHDL-AMS Architecture Body Revisited ♦ Using a simple simultaneous statement and an overloaded function architecture Simult of WeightedSummer is ...
T. time is limited by the specified slopes. Default for max_falling_slope is max_rising_slope, default for max_rising_slope is infinity. @8u vrÃF7hxhyh Ã6H9rrÃ@Hr 968((ÃWC9G6HTÃU vhy VHDL AMS Outline ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Introduction Brief Overview of VHDL-AMS Basic Concepts: DAEs Systems with Conservation Semantics: Diode Mixed Technology: Diode with Self Heating Piecewise Defined Behavior: Compressor,Voltage Limiter Procedural Modeling: Weighted Summer Signal-Flow Modeling: Adder-Integrator, Conversions Solvability: Voltage Source, Signal Flow Amplifier Initial Conditions: Capacitor Implicit Quantities Mixed-Signal Modeling: Comparators, D/A Converter VHDL-AMS Model Execution Discontinuities: SCR, Voltage Limiter, Bouncing Ball Time-Dependent Modeling: Sinusoid Voltage Source Frequency Domain Modeling: Current Source, Filter Noise Modeling: Resistor, Diode Conclusion @8u vrÃF7hxhyh Ã6H9rrÃ@Hr 968((ÃWC9G6HTÃU vhy VHDL AMS Ideal Comparator VHDL-AMS Entity Declaration entity Comparator is generic (vthresh: REAL); -- threshold port (terminal ain, ref: electrical; signal dout: out BOOLEAN); end entity Comparator; ♦ Keyword signal is optional but indicates intent: • Interface terminals ain and ref • Interface signal dout @8u vrÃF7hxhyh Ã6H9rrÃ@Hr 968((ÃWC9G6HTÃU vhy VHDL AMS Ideal Comparator VHDL-AMS Architecture Body architecture Ideal of Comparator is quantity vin across ain to ref; begin dout <= vin’above(vthresh); end architecture Ideal; ♦ Threshold crossing detected with Q’Above(E), a boolean signal that • is FALSE when the value of quantity Q is below threshold E • is TRUE when the value of quantity Q is above threshold E ♦ Q must be a scalar quantity, E must be an expression of the same type as Q ♦ An event occurs on signal Q’Above(E) at the exact time of the threshold crossing ♦ A process can be sensitive to Q’Above(E), since it is a signal @8u vrÃF7hxhyh Ã6H9rrÃ@Hr 968((ÃWC9G6HTÃU vhy VHDL AMS Comparator with Hysteresis ♦ Conversion of electrical quantity to std_logic signal ♦ Hysteresis dout ‘1’ ‘X’ ‘0’ vin vlo vhi • dout becomes ‘X’ if vin stays in transition region for longer than the specified timeout @8u vrÃF7hxhyh Ã6H9rrÃ@Hr 968((ÃWC9G6HTÃU vhy VHDL AMS Comparator with Hysteresis State Diagram one YLQ !