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Extra info for ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis for the New Generation of VLSI ASIC Technologies (Workshop Proceedings)

Sample text

4 .. . .. ..... :7 : 4. 6... . .. . .......... ........... 9 . ... ' ... ................... ........ I... I................... ............. ............ ............ ''...... '........... 6...... .. . . . . ....................... input node at root I output nodes ( 4, 6,7, 9, 11, 12 1 # indicates the sequence of an edge being added to the tree. Figure 6: An example of the execution of the presented layout algorithm. thickness, to.

Elepath(no,n,) We can extend the t ED function to entire trees by defining tED(T(N)) = max tED(ni). , are proportional to the length of ej, the delay tED(ni) is quadratic in the length of the n0 -ni path and also linear in total wirelength (which is proportional to C1 ). Because of its relatively simple form, Elmore delay can be calculated in 0(k) time, as noted by Rubinstein et al. [19]. , versus unit wire resistance) can have a significant effect on the topology of the optimal routing tree: if rd is large, the optimal routing tree is a minimum cost spanning tree, while if rd is close to 0, the ORT will possess a "star" topology.

1% greater than optimal, while MSTs have delay 124% greater than optimal on average. 6% above optimal. 1% difference obtained for 4Note that this observation assumes constant loading capacitances, unit resistances, and unit capacitances for the Elmore model. 5 The SPT construction is the tree which minimizes cost subject to each source/sink path having minimum length.

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